The present invention relates generally to a CCD image sensing apparatus and, more particularly, to an interline transfer CCD image sensing apparatus with multiple outputs for high framing rate.
The state of the art of interline transfer CCD image sensing apparatus is well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. Patents:
U.S. Pat. No. RE 31,612 issued to Sauer on 26 June 1984; PA1 U.S. Pat. No. 3,890,633 issued to Kosonocky et al on 17 June 1975; PA1 U.S. Pat. No. 3,913,077 issued to Erb on 14 Oct. 1975; and PA1 U.S. Pat. No. 4,613,402 issued to Losee et al on 23 Sept. 1986.
The Sauer patent is directed to CCD input circuits which include a floating diffusion, a source supplying a controllable amount of charge to the floating diffusion and a charge coupled device (CCD) reference register for periodically removing a fixed amount of charge from the floating diffusion. A feedback circuit sense the average voltage at the floating diffusion and adjusts the controllable amount of charge supplied to the diffusion to maintain its average voltage-level constant
The Kosonocky patent describes a charge-coupled, light-sensing array, in which every third charge storage electrode is maintained at a direct voltage level. Charge is shifted between such electrodes by two voltage phases, each varying in amplitude from a level lower then to a level greater than said direct voltage level, applied to two intervening charge storage electrodes, respectively.
The Erb patent discloses a CCD memory device having on a single chip a parallel multi-channel storage section into which data is fed by a serial input register and from which data is read by a serial output register. Although at least two storage electrodes are needed throughout the memory to store each bit of information, the total number of such electrodes required in the input and output registers is greatly reduced by alternately storing the input and output bits at even and odd numbered storage electrodes of the input and output registers, so that each storage electrode may serve a separate channel of the parallel storage section.
The Losee et al patent discusses a method for accurately aligning the edge of the implanted barrier in a semiconductor substrate with the edge of its overlying electrode, which is necessary to the making of CCD's. This position is less sensitive to processing parameters.
In interline transfer type imaging devices, photogenerated charge is collected on a PN junction or under the gate of a photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit. In an area array of such photocharge collection sites it is necessary to transfer the collected photocharge, first to a vertical shift register and then to a horizontal shift register, finally, reaching a charge sensitive detector or amplifier.
In prior art, as indicated schematically in FIG. 1, all of the photocharge is read out through a single charge sensing circuit. The maximum rate at which such circuit can operate is typically less than 20 MHz, and in turn limits the frame rate at which the detector may be operated.
Commercially-available detectors in the prior art are subjected to this limitation in the maximum framing rate, this limitation can be overcome by the use of multiple shift register outputs. When many outputs are required, it becomes difficult to make contact between the package electrodes and the die output electrodes (bondpads) because of a lack of space. As the detector size and number of outputs increases, this problem becomes more severe. Thus, it is advantageous to have the outputs distributed equally about the die edge, and to match the pitch of the detector such that an increase in resolution does not reduce the spacing between bondpads.
When operating with low photosignal levels, interline transfer CCD detectors made with conventional photodiodes suffer from signal loss due to the lag mechanism. To overcome this problem, a special Pinned Photodiode has been disclosed as in B. C. Burkey, W. C. Chang, J. Littlehale, T. J. Lee, T. J. Tredwell, J. P. Lavine, E. A. Trabka, The Pinned Photodiode for an Interline-Transfer CCD Image Sensor, Proc. IEEE International Electron Devices Meeting, Dec. 9-12, 1984, p. 28.
When operating at high clocking speeds, and with long phase lengths, the transfer of charge in CCD shift registers become inefficient because of inadequate time for the charge to diffuse out of the past storage phase and into the next storage phase. In this case, the transfer efficiency may be improved by a design and fabrication process that results in electric fields within each phase that drifts the stored charge rapidly forward into the next phase. This method has been disclosed in J. Hynecek, Design and Performance of a High-Resolution Image Sensor for Color TV Applications, IEEE Trans. Electron. Dev., Vol. ED-32, (1985), p. 1421.
Prior interline CCD photodiode detectors have used a four-phase or pseudo-two phase CCD interline (vertical) shift register. These approaches require an interlaced readout of the image. For applications with time varying scene illumination, the interlaced readout results in the field flicker artifact. The patent of Losee et al U.S. Pat. No. 4,613,402 discloses a true-two phase CCD gate structure permitting non-interlaced readout of array detectors.
When operating at high data rates it is advantageous to use charge sensing amplifier circuits that have high sensitivity and low noise. The prior art, such as disclosed in E. G. Stevens, T-H. Lee, D. N. Nichols, C. N. Anagnostopoulos, B. C. Burkey, W. C. Chang, T. M. Kelly, P. Khosla, D. L. Losee, T. J. Tredwell, A 1.4 Million Element CCD Image Sensor, Proc. Int. Solid State Circuits Conf., Feb. 25, 1987, p. 114, for example, uses a floating diffusion sensing node with two following source follower stages.
While the above-cited references are instructive, there still remains a need to provide a method to measure the surface temperature of reacting and nonreacting materials. The present invention is intended to satisfy that need.